1. Field
Embodiments of the present invention relate to the fabrication of interconnect structures in microelectronic devices. In particular, embodiments of the present invention relate to a method for copper deposition to fill narrow and high aspect ratio openings formed in low-k dielectric layers during the fabrication of interconnect structures.
2. State of the Art
The fabrication of microelectronic devices involves forming electronic components on microelectronic substrates, such as silicon wafers. These electronic components may include transistors, resistors, capacitors, and the like, with intermediate and overlying metallization patterns at varying levels, separated by dielectric materials, which interconnect the electrical components to form integrated circuits. The metallization patterns are generally referred to as “interconnects”.
One process used to form interconnects is known as a “damascene process”. In a typical damascene process, a photoresist material is patterned on a dielectric material and the dielectric material is etched through the photoresist material patterning to form a hole or a trench or a via (hereinafter collectively referred to as “an opening” or “openings”). The photoresist material is then removed (typically by an oxygen plasma) and the opening is then filled with a conductive material (e.g., such as a metal or metal alloys). The filling of the opening may be accomplished by either physical vapor deposition, chemical vapor deposition, or electroplating, as will be understood to those skilled in the art. The term “interconnect” is defined herein to include all interconnection components including trenches and vias filled with conductive material.
A barrier layer is typically deposited on the dielectric material within the opening to prevent diffusion of the conductive material. For example, as known, copper is one preferred conductive material. Copper diffuses quickly and easily into adjacent layer, thus, a diffusion layer is needed to prevent such diffusion. Additionally, a seed layer is deposited on the barrier layer. The seed layer acts as an activation site for a conductive material to form thereon.
The resulting structure is planarized, usually by a technique called chemical mechanical polish (CMP) or by an etching process, which removes the conductive material, which is not within the opening, from the surface of the dielectric material, to form the interconnect. As is understood by those skilled in the art, a variety of vias and trenches may be formed in the various dielectric material layers to electrically connect to one another and/or to various electronic components. In another damascene process, known as a “dual damascene process”, trenches and vias are substantially simultaneously filled with the conductive material with a single deposition.
As the density of integrated circuits within microelectronic devices continues to increase with each successive technology generation, the interconnects become smaller and their aspect ratios (i.e., the ratio of depth to width) may increase. As shown in FIGS. 1-2, a problem with small size and/or high aspect ratios is that a conductive material 402 can build up at an opening 404 proximate a first surface 406 of a dielectric material 408 (i.e., the “mouth” 412 of the opening 404) during deposition. A barrier layer 410 is also present, as will be understood to those skilled in the art.
The “build-up” or “overhang” (illustrated within dashed circle 414) blocks the path of the conductive material 402 deposition and, as shown in FIG. 3, often can result in voids 416 forming within the conductive material 402 in the opening 404 (shown in FIGS. 1-2). Typically, copper is used for filling the opening 404 and a seed layer ( not labeled) is often formed over the barrier layer 410 prior to the deposition of the copper to form the interconnect. Also, for such a small opening, the barrier layer 410 and the seed layer need to be formed conformally to facilitate uniform deposition of the copper filling. Current methods of forming the seed layer tends to result in insufficient sidewall coverage or non-continuous seed layer that also produces voids 416 during opening filling process. Increasing the seed layer thickness also results in the overhang 414.
FIG. 3 illustrates an interconnect 418 is formed after the conductive material 402 is deposited and planarized. The voids 416 can have different sizes, distributions, and locations within the interconnect 418. For example, some voids 416 may be so large that they effectively break the conductive path of the interconnect 418, which may result in the failure of the microelectronic device, thereby having an immediate impact on yield. Additionally, the voids 416 may also be small, which may have an immediate impact by restricting the flow of electrons along the interconnect 418 and/or may have a negative impact on the long-term reliability of the microelectronic device.
Current technology attempts to deal with the void and overhang problem by modifying the seed layer deposition process. For example, after depositing the seed layer, the seed material is re-flown (by using a thermal treatment process that causes the material to re-flow and reform) to improve conformality of the seed layer. Other process includes multiple flash deposition steps or increasing a plasma power used in depositing the seed layer.
Additionally, as mentioned, CMP is used for planarizing the deposited copper material. However, for a low-k dielectric, the mechanical integrity of the dielectric layer may be weakened by the process. Thus, the conventional process used to planarize the conductive material has a high tendency of damaging the dielectric layer.
It remains that there is no solution for uniformly filling the small features such as high aspect ratio trenches or vias typically referred to as features of 32 nm technology node. There also remains no solution for a planarizing method that minimizes damages to the dielectric layer.
Therefore, it would be advantageous to develop techniques to effectively fill openings, while reducing or substantially eliminating void formation during the fabrication of interconnects for microelectronic devices.